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2X20 LCD Compatible VFD Module To:
20T202DA1E (Rev. 3.0)
SPECIFICATION
Rev. 3.0
Application:
VACUUM FLUORESCENT DISPLAY MODULE
Model No.: 20T202DA1E
Rev. No. Tentative Rev. 1.0
Issued Date Oct. 16, 1998 Jan. 07, 2000 First Edition
Revision Descriptions * Change of AC Characteristics (i80 bus interface) - tCYC(/WR) =166ns 200ns - tCYC (/RD) =166ns 200ns - tWH (/RD) =70ns 100ns * Change of Operating and Storage Temperature - Topr: (-20 ~ +75) (-40 ~ +85 ) - Tstg: (-40 ~ +85) (-50 ~ +85) * Change of Power On Reset Timing - tOFF:100ms(Min.) 1ms(Min.) - tr:1ms(Max.) 1us(Min.) * Change of System Block Diagram * Change of Outer Dimensions * Addition of Index Page etc * Change of Production Plant (SDI SSVD) * Addition of Initialization and Data Set Example * Change of Document Formation
Remark All Pages Page - 5
Page - 4
Rev. 2.0
Oct. 16, 2002
Page - 5
Rev. 3.0
Apr. 10, 2005
Page - 7 Page - 8 Page - 2 Page - 3 Page - 17 All Pages
Issued by
Customer's Approval
Checked by
Approved by
Page - 1 of 17
2X20 LCD Compatible VFD Module
20T202DA1E (Rev. 3.0)
~~~~~~~~~~~~~~~~ Index ~~~~~~~~~~~~~~~~
1. SCOPE................................................................................................................................................................... Page - 3 2. FEATURES........................................................................................................................................................... Page - 3 3. PRECAUTIONS.....................................................................................................................................................Page - 3 4. PRODUCT SPECIFICATIONS....................................................................................................................... Page - 4 4.1 Type.................................................................................................................................................................. Page - 4 4.2 Outer Dimensions, Weight............................................................................................................................. Page - 4 4.3 Environment Conditions................................................................................................................................. Page - 4 4.4 Absolute Maximum Ratings........................................................................................................................... Page - 4 4.5 Recommended Operating Conditions............................................................................................................. Page - 4 4.6 DC Characteristics............................................................................................................................................. Page - 4 4.7 Timing Chart and AC Characteristics.............................................................................................................. Page - 5 4.7.1 Power-on Reset and/or RESET Signal Timing...................................................................................... Page - 5 4.7.4 M68 Type CPU Bus Write-in Timing.................................................................................................... Page - 5 4.7.5 M68 Type CPU Bus Read-out Timing................................................................................................... Page - 5 4.7.2 i80 Type CPU Bus Write-in Timing....................................................................................................... Page - 6 4.7.3 i80 Type CPU Bus Read-out Timing......................................................................................................Page - 6 4.8 Connector Pin Assignment................................................................................................................................Page - 6 4.9 System Block Diagram......................................................................................................................................Page - 7 4.10 Connector through Hole Location.................................................................................................................. Page - 7 4.11 Outer Dimensions............................................................................................................................................ Page - 8 4.12 Pattern Details.................................................................................................................................................. Page - 8 5. FUNCTION DESCRIPTIONS.......................................................................................................................... Page - 9 5.1 Registers in VFD Controller.......................................................................................................................... Page - 9 5.1.1 Busy Flag (BF)....................................................................................................................................... Page - 9 5.1.2 Address Counter (ACC)....................................................................................................................... Page - 9 5.1.3 Display Data RAM (DD-RAM)........................................................................................................... Page - 9 5.1.4 Character Generator ROM (CG-ROM)............................................................................................... Page - 9 5.1.5 Character Generator RAM (CG-RAM)............................................................................................... Page - 9 * CG-RAM Font Design Example............................................................................................................... Page - 10 5.2 Interfacing to the MPU................................................................................................................................... Page - 11 5.3 MPU Type Select Function............................................................................................................................... Page - 11 5.4 Reset Function....................................................................................................................................................Page - 11 5.4.1 Power-on Reset.........................................................................................................................................Page - 11 5.4.2 External Reset........................................................................................................................................ Page - 11 6. INSTRUCTIONS................................................................................................................................................... Page - 12 6.1 Outline................................................................................................................................................................ Page - 12 6.2 Instructions Descriptions.................................................................................................................................. Page - 13 6.2.1 Display Clear............................................................................................................................................ Page - 13 6.2.2 Cursor Home............................................................................................................................................ Page - 13 6.2.3 Entry Mode Set...................................................................................................................................... Page - 13 6.2.4 Display ON/OFF................................................................................................................................... Page - 14 6.2.5 Cursor/Display Shift................................................................................................................................ Page - 15 6.2.6 Function Set.............................................................................................................................................. Page - 15 6.2.7 Set CG-RAM Address............................................................................................................................. Page - 15 6.2.8 Set DD-RAM Address........................................................................................................................... Page - 15 6.2.9 Read Busy Flag and Address...................................................................................................................Page - 15 6.2.10 Write Data to CG or DD-RAM.......................................................................................................... Page - 15 6.2.11 Read Data from CG or DD-RAM.................................................................................................... Page - 16 6.3 Example of Initialization after Power ON....................................................................................................... Page - 16 * Character Code Table (CG-RAM & CG-ROM)............................................................................................ Page - 17 Page - 2 of 17
2X20 LCD Compatible VFD Module
20T202DA1E (Rev. 3.0)
1. SCOPE
* This specification applies to VFD module (Model No.: 20T202DA1E) manufactured by Samsung SDI or SSVD(Shanghai Samsung Vacuum Devices).
2. FEATURES
* LCD Compatible: Drop-in-replacement (Same Interface and Mechanical Dimension as LCD Module). * High Quality, Attractive and Readable Display: 5*7 Dot Matrix Type Vacuum Fluorescent Display. * Compact and Lightweight: Flat Panel (VFD) and Surface Mount Technology. * +5V single power supply. * Brightness Level: Adjustable into 4 Levels (25%, 50%, 75% and 100%) by Software Command. * Support CG-RAM Fonts and CG-ROM: 8 User-definable Characters (Volatile) and 240 Masked CG-ROM Fonts.
3. PRECAUTIONS
* Avoid applying excessive shock or vibration beyond the specification for the VFD module. * Since VFDs are made of glass material, careful handling is required. i.e. Direct impact with hard material to the glass surface (especially exhaust tip) may crack the glass. * When mounting the VFD module to your system, leave a slight gap between the VFD glass and your front panel. The module should be mounted without stress to avoid flexing of the PCB. * Avoid plugging or unplugging the interface connection with the power on, otherwise it may cause the severe damage to input circuitry. * Slow starting power supply may cause non-operation because one chip MCU won't be reset. * Exceeding any of maximum ratings may cause the permanent damage. * Since the VFD modules contain high voltage source, careful handling is required during powered on. * When the power is turned off, the capacitor does not discharge immediately. The high voltage applied to the VFD must not contact to the ICs. And the short-circuit of mounted components on PCB within 30 seconds after power-off may cause damage to those. * The power supply must be capable of providing at least 5 times the rated current, because the surge current can be more than 5 times the specified current consumption when the power is turned on. * Avoid using the module where excessive noise interference is expected. Noise may affects the interface signal and causes improper operation. And it is important to keep the length of the interface cable less than 50cm. * Since all VFD modules contain C-MOS ICs, anti-static handling procedures are always required.
Page - 3 of 17
2X20 LCD Compatible VFD Module
20T202DA1E (Rev. 3.0)
4. PRODUCT SPECIFICATIONS
4.1 Type Type (Module Name) Character Format Number of Digits 20T202DA1E 5 * 7 Dot Matrix with Cursor 40 (20 Digits * 2 Lines)
4.2 Outer Dimensions, Weight (Refer to the Fig.-8 & 9 on Page-8 for details) Parameter Symbol Specification Outer Dimensions W*H*t 116.0 * 37.0 * 15.0 Panel Size W*H 95.0 * 25.0 Display Size W*H 70.8 * 11.5 Character Size CW * CH 2.4 * 5.4 Character Pitch CP(x) * CP(y) 3.6 * 6.1 Dot Size DW * DH 0.4 * 0.5 Display Color x= 0.250, y = 0.439 (Green) Weight Approx. 80 4.3 Environment Conditions Parameter Operating Temperature Storage Temperature Humidity (Operating) Humidity (Non-operating) Vibration (10 ~ 55 Hz) Shock 4.4 Absolute Maximum Ratings Parameter Supply Voltage Input Signal Voltage 4.5 Recommend Operating Conditions Parameter Supply Voltage Input Signal Voltage
Unit mm mm mm mm mm mm g
Symbol Topr Tstg Hopr Hstg -
Min. -40 -50 0 0 -
Max. +85 +85 85 90 4 40
Unit o C o C % % G G
Symbol VCC VIS
Min. -0.5 -0.5
Max. 6.0 VCC+0.5
Unit VDC VDC
Symbol VCC VIS
Min. 4.5 0
Typ. 5.0 -
Max. 5.5 VCC
Unit VDC VDC
4.6 DC Characteristics (Ta = +25 oC, VCC = 5.0VDC) Parameter Symbol Supply Current *1) ICC "H" Level Logic Input Voltage VIH "L" Level Logic Input Voltage VIL "H" level Input Current (VIN = VCC) *2) IIH "L" level Input Current (VIN = 0VDC) IIL
Min. Typ. Max. 150 220 0.7VCC 0.3VCC 20 500 -1.0 102 204 Luminance L (350) (700) *1) The in-rush current can be approx. 5 times the specified supply current at power on. *2) A 10k-ohm resistor is pulled-up on each input signals for TTL compatibility.
Unit mA VDC VDC uA mA ft-L (cd/m2)
Page - 4 of 17
2X20 LCD Compatible VFD Module
20T202DA1E (Rev. 3.0)
4.7 Timing Chart and AC Characteristics 4.7.1 Power-on Reset Timing
tOFF(VCC) 1ms/Min.
VCC
tr(VCC) 1us/Min.
/WR
tWAIT (*) 100us/Min.
t/RST 500ns/Min.
/RST
(*) Note-2: Internal Reset Timing Interval
Fig.-1. Power-on Reset and /RST Signal Timing
4.7.2 M68 type CPU Bus Interface Timing
tSU(RS,/R/W) tH (RS,R/W) 10ns/Min. tCYC(E) 500ns/Min.
R/W
20ns/Min.
RS
tWH (E) 230ns/Min. TWL (E) 230ns/Min.
E
tSU (DATA) 80ns/Min. tH (DATA) 10ns/Min.
DB0~DB7
Valid Data Input Fig.-2. Data Write-in Timing for M68 Interface Mode
R/W
tSU(RS,/R/W) 20ns/Min. tCYC(E) 500ns/Min.
tH (RS,R/W) 10ns/Min.
RS
tWH (E) 230ns/Min. TWL (E) 230ns/Min.
E
TDELAY (DATA) 160ns/Max. tH (DATA) 5ns/Min.
DB0~DB7
Effective Data Output Fig.-3. Data Read-out Timing for M68 Interface Mode
Page - 5 of 17
2X20 LCD Compatible VFD Module 4.7.3 i80 type CPU Bus Interface Timing
20T202DA1E (Rev. 3.0)
tCYC(/WR) 200ns/Min.
RS
tSU(RS) 10ns/Min. tWL (/WR) tH (RS) 10ns/Min. 30ns/Min. tSU (DATA) 30ns/Min.
/WR
tWH (/WR) 100ns/Min. tH (DATA) 10ns/Min.
DB0~DB7
Valid Data Input Fig.-4. Data Write-in Timing for i80 Interface Mode
tCYC(/WR) 200ns/Min.
RS
tSU(RS) 10ns/Min. tWL (/RD) tH (RS) 10ns/Min. 70ns/Min. TACC (DATA) 70ns/Max.
/RD
tWH (/RD) 100ns/Min. TOH (DATA) 5ns/Min.
DB0~DB7
Effective Data Output Fig.-5. Data Read-out Timing for i80 Interface Mode
4.8 Connector Pin Assignment 14 through holes are prepared for power supply and signal interface. A connector may be able to solder to the holes. Location and dimensions are shown at Fig.-7.
Pin No. 1 2 3 4 5 Symbol GND VCC I/O Input Input Input Descriptions Ground Terminal Supply Power Terminal Reserved for Reset Signal (Active Low) If a user would like to use external reset by using this terminal then he must short-circuit the jumper switch, JP1. i.e. /RST is signal can be used when JP1 is closed. Register Select ("0"; Instruction Register, "1"; Data Register) When M68 interface mode is selected (JP0; Open), this pin is to be data IN/OUT select pin. ("0"; Data Write-in, "1"; Data Read-out) When i80 interface mode is selected (JP0; Short), this pin is to be WRITE enable pin. (Writes data at rising edge of this signal.) When M68 mode is selected (JP0; Open), this pin is to be Read/Write enable. (Writes data at the falling edge and Reads data at the rising edge.) When i80 mode is selected (JP0: Short), this signal is to be READ enable pin. (When this pin is low level, logic "0", the effective data is output to data bus.) These pins are used for data IN/OUT pin. When select 4 bits transfer mode, just DB4 (pin #11) to DB7 (pin #14) are used. Data are stored sequentially, with data transmitted first stored in upper bits (MSB). The DB7 (pin#14) signal can be used for BUSY flag out when RS="0" and R/W="1" for M68 read-out mode.
/RST (*)
RS R/W (/WR)
6 7 8 9 10 11 12 13 14
E (/RD) DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
Input
I/O
Page - 6 of 17
2X20 LCD Compatible VFD Module 4.9 System Block Diagram
20T202DA1E (Rev. 3.0)
72 VDD1 Rup*4 (10kOhm) A1~A72 20 G1~G20 #6 #5 #4 #3 JP1 Jumper Switch for External Reset /RST E(/RD) R/W(/WR) RS Grids Anodes
E R/W RS /RST
VFD Panel (2x20 Digits)
VFD Controller
VSS Rup*8 (10kOhm) MPU
JP0 Jumper Switch to Select Interfacing Mode F1 F2
DB0~DB7
#7~14
8
D0~D7
VDD2
VCC GND
#2 #1
DC/DC Converter
Fig.-6 System Block Diagram
4.10 Through-hole Location for Connector Assembly
#14
#13
Soldering Hole Diameter: 1.0mm
#2
#1
(Unit: mm) Fig.-7 Connector Through-hole Location
Page - 7 of 17
2X20 LCD Compatible VFD Module 4.11 Outer Dimensions
20T202DA1E (Rev. 3.0)
Unit: mm Tolerance unless otherwise specified: * Mounting Hole Size: +/- 0.3 * Length: Range < 10: +/- 0.5 Range > 10: +/- 1.0
Fig.-8 Drawings for Outer Dimensions
4.12 Pattern Details
Fig.-9 Drawings for Pattern Details
Page - 8 of 17
2X20 LCD Compatible VFD Module
20T202DA1E (Rev. 3.0)
5. FUNCTION DESCRIPTIONS
5.1 Registers in VFD Controller The VFD controller has two 8-bit registers, an instruction register (IR) and a data register (DR). IR stores instruction codes, such as display clear and cursor shift, and address information for DD-RAM and CG-RAM. The IR can only be written from the host MPU. DR temporarily stores data to be written into DD-RAM or CG-RAM and temporarily stores data to be read from DD-RAM or CG-RAM. Data written into the DR from the MPU is automatically written into DD-RAM or CG-RAM by an internal operation. The DR is also used for data storage when reading data from DD-RAM or CG-RAM. When address information is written into the IR, data is read and then stored into the DR from DD-RAM or CG-RAM by internal operation. Data transfer between MPU is then completed when the MPU reads the DR. After the read, data in DD-RAM or CG-RAM at the next address is sent to the DR for the next read from the MPU. By the register selector (RS) signal, these two registers can be selected. * Truth Table for Register Selection M68 i80 RS R/W /RD /WR 0 0 1 0 0 1 0 1 1 0 1 0 1 1 0 1
Operation IR write as an internal operation (display clear, etc.) Read busy flag (DB7) and address counter (DB0 to DB6) DR write as an internal operation (DR to DD-RAM or CG-RAM) DR read as an internal operation (DD-RAM or CG-RAM to DR)
5.1.1 Busy Flag (BF) When the busy flag is 1, the controller is in the internal operation mode, and the next instruction will not be accepted. When RS = 0 and R/W = 1, the busy flag is output to DB7. The next instruction must be written after ensuring that the busy flag is 0. 5.1.2 Address Counter (ACC) The address counter (ACC) assigns addresses for both DD-RAM and CG-RAM. When an instruction of address is written into the IR, the address information is sent from the IR to the ACC. Selection of either DD-RAM or CG-RAM is also determined concurrently by the instruction. After writing into (reading from) DD-RAM or CG-RAM, the ACC automatically increased by 1 (decreased by 1). The ACC contents are then output to DB0 to DB6 when RS = 0 and R/W = 1. 5.1.3 Display Data RAM (DD-RAM) Display data RAM (DD-RAM) stores display data represented in 8-bit character codes. The area in DD-RAM that is not used for display can be used as general data RAM. See below Table for the relationships between DD-RAM addresses and positions on the VFD. * The Relationships Between DD-RAM Addresses and Positions on the VFD 1st Column 2nd Column 3rd Column ......... 19th Column 1st ROW 00 Hex 01 Hex 02 Hex ......... 12 Hex 2nd ROW 40 Hex 41Hex 42 Hex ......... 52 Hex
20th Column 13 Hex 53 Hex
5.1.3 Character Generator ROM (CG-ROM) The character generator ROM (CG-ROM) generates character patterns of 5*7 dots from 8-bit character codes. It can generate 240 kinds of 5*7 dot character patterns. The character fonts are shown on the Fig.-10. The character codes 00H to 0FH are allocated to the CG-RAM. 5.1.4 Character Generator RAM (CG-RAM) The CG-RAM stores the pixel information (1=pixel on, 0=pixel off) for the eight user-definable 5*7 characters including cursor. Valid CG-RAM addresses are 00H to 3FH. CG-RAM not being used to define characters can be used as general purpose RAM (lower 5 bits only). Character codes from 00H to 07H (or 08H to 0FH) are assigned to the user-definable characters (refer to Appendix-1 for Character Font Tables). The table on next page shows the relationship between the character codes, CG-RAM addresses, and CG-RAM data for each user-definable character.
Page - 9 of 17
2X20 LCD Compatible VFD Module
20T202DA1E (Rev. 3.0)
* Relationship Between CG-RAM Addresses, Character Code (DD-RAM) and 5*7 (with cursor) Dot Character Patterns (CG-RAM data).
Character Codes (DD-RAM) D7 D6 D5 D4 D3 D2 D1 D0 CG-RAM Address A5 A4 A3 A2 A1 A0 000 001 010 011 000 100 101 110 111 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D7 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * D6 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * CG-RAM Data D5 D4 D3 D2 *011 *100 *100 *111 *100 *100 *100 *0** *111 *100 *100 *111 *100 *100 *111 *0** *011 *001 *001 *001 *001 *001 *011 *0** *001 *010 *111 *010 *111 *010 *001 *0** Pattern Example D1 1 0 0 1 0 0 0 * 1 0 0 1 0 0 1 * 1 0 0 0 0 0 1 * 1 0 0 0 0 0 1 * D0 0 1 1 1 1 1 1 * 0 1 1 0 1 1 0 * 0 0 0 0 0 0 0 * 0 0 0 0 0 1 0 * Hex. 0EH 11H 11H 1FH 11H 11H 11H 00H 1EH 11H 11H 1EH 11H 11H 1EH 00H 0EH 04H 04H 04H 04H 04H 0EH 00H 06H 08H 1CH 08H 1CH 09H 06H 00H
CG-RAM #1 (Example of "A")
0
0
0
0
*
0
0
0
Cursor Position
CG-RAM #2 (Example of "B")
0
0
0
0
*
0
0
1
0
0
1
Cursor Position
CG-RAM #3 (Example of "I")
0
0
0
0
*
0
1
0
0
1
0
Cursor Position
CG-RAM #4 (Example of Euro Currency Symbol)
0
0
0
0
*
0
1
1
0
1
1
Cursor Position
1) *: Indicates no effect (Don't care). 2) Character code bits 0 to 2 correspond to CG-RAM address bits 3 to 5 (3 bits: 8 types). 3) CG-RAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. If bit 4 of the 8th line data is 1, 1 bit will light up the cursor regardless of the cursor presence. 4) Character pattern row positions correspond to CG-RAM data bits 0 to 4 (bit 4 being at the left). 5) CG-RAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bit 3 has no effect, the "A" display example above can be selected by either character code 00H or 08H. 6) " 1" for CG-RAM data corresponds to display selection and " 0" to non-selection.
Page - 10 of 17
2X20 LCD Compatible VFD Module
20T202DA1E (Rev. 3.0)
5.2 Interfacing to the MPU This VFD module MPU interface operates in two 4-bit (DB4 to DB7) in M68 type. For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. When to use 4-bit parallel data transfer, DB0 to DB3 keep "H" or "L" ("L" in this module). The data transfer between the VFD module and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer the four high order bits (D4 to D7) are transferred before the four low order bits (D0 to D3). RS
E
IR7 IR6 IR5 IR4
DB7 DB6 DB5 DB4
IR3
IR2 IR1 IR0
D7 D6 D5 D4
D3 D2 D1 D0
IR7 IR6 IR5 IR4
IR3
IR2 IR1 IR0
D7 D6 D5 D4
D3 D2 D1 D0
D7 D6 D5 D4
D3 D2 D1 D0
Instruction Register Character Code Write-in Write-in
Instruction Register Write-in
Character Code Write-in
Character Code Write-in
Fig.-11 4-bit Transfer Example (M68)
5.3 Reset Function 5.3.1 Power-on Reset Function An internal reset circuit automatically initializes the module when the power is turned on. The following instructions are executed during the initialization. (1) Display clear * Fill the DD-RAM with 20H (Space Code) (2) Set the address counter to 00H * Set the address counter (ACC) to point DD-RAM. (3) Display on/off control: * D = 0...................................Display off * C = 0................................... Cursor off * B = 0................................... Blinking off (4) Entry mode set: * I/D = 1................................ Increment by 1 * S = 0....................................No shift (5) Function set * IF = 0 ................................. 4-bit interface data * N = 1 ..................................2-line display * BR0 =0, BR1 =0.................Brightness = 100% (6) CPU interface type * MPU = 1.............................M68 type 5.3.2 Software Reset When the user want to RESET the module without turning off the power supply, input both "RST" and "Add" bit high level while giving low level to the others. Please refer to "Fig.-3 CLK and Reset Command Write-in Detail" for particular information about software reset. The reset function will be the same as the power-on reset.
Page - 11 of 17
2X20 LCD Compatible VFD Module
20T202DA1E (Rev. 3.0)
6. INSTRUCTIONS
6.1 Outline Only the instruction register (IR) and the data register (DR) of the VFD controller can be controlled by the user's MPU. Before starting the internal operation of the controller, control information is temporarily stored into these registers to allow different data transfer mode, display line setting and dimming control etc. The internal operation of the controller is determined by signals sent from the MPU. These signals, which include register selection signal (RS), write enable signal (E), and the data bus (DB4 to DB7), make up the controller instructions. There are four categories of instructions which are: * Designate controller functions, such as display format, data length, etc. * Set internal RAM addresses. * Perform data transfer with internal RAM. * Perform miscellaneous functions. Normally, instructions that perform data transfer with internal RAM are used the most. However, auto-incrementation by 1 (or auto-decrementation by 1) of internal RAM addresses after each data write can lighten the program load of the MPU. Since the display shift instruction can perform concurrently with display data write, the user can minimize system development time with maximum programming efficiency. *Instruction List
Instructions Display Clear Cursor Home RS 0 0 Instruction Code D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 1 D0 1 * Descriptions Clears all display and sets DD-RAM address 00 in address counter. Sets DD-RAM address 0 in ACC. Also returns the display being shifted to the original position. DD-RAM contents remain unchanged. Sets the cursor direction and specifies display shift. These operations are performed during writing/reading data. Sets all display ON/OFF (D), cursor ON/OFF (C), cursor blink of character position (B). Shifts display or cursor, keeping DD-RAM contents. Sets data length (IF), number of display lines (N), Set brightness level (BR1,BR0) Sets the CG-RAM address. Sets the DD-RAM address. Writes data into CG-RAM or DD-RAM. * IF = 1: 8-bit Operation * IF = 0: 4-bit Operation * N = 1: 2 Lines Display * N = 0: 1 Line Display * BR1, BR0 = 00: 100%, 01: 75%, 10: 50%, 11: 25%
Entry Mode Set Display ON/OFF Control Cursor or Display Shift Function Set CG-RAM Address Set DD-RAM Address Set Data Writing to CG- or DD-RAM REMARKS: * DD-RAM: Display Data RAM * CG-RAM: Character Generator RAM * ACG: CG-RAM Address * ADD: DD-RAM Address * ACC: Address Counter
0 0 0 0 0 1 1
0 0 0 0 0 1
0 0 0 0 1
0 0 0 1
0 0 1 IF
0 1
1 D
I/D C *
S B *
S/C R/L N *
BR1 BR0
ACG (CG-RAM Address) ADD (DD-RAM Address) Character Code
* I/D = 1: Increment * I/D = 0: Decrement * S = 1: Display Shift Enabled * S = 0: Cursor Shift Enabled * S/C = 1: Display Shift * S/C = 0: Cursor Move * R/L = 1: Shift to the Right * R/L = 0: Shift to the Left
Page - 12 of 17
2X20 LCD Compatible VFD Module 6.2 Instruction Descriptions 6.2.1 Display Clear
D7 0 RS = 0 D6 0 D5 0 D4 0 D3 0
20T202DA1E (Rev. 3.0)
D2 0
D1 0
D0 1
Hex. Range 01H
This instruction (1) Fills all locations in the display data RAM (DD-RAM) with 20H (Blank-character). (2) Clears the contents of the address counter (ACC) to 00H. (3) Sets the display for zero character shifts (returns original position). (4) Sets the address counter (ACC) to point to the DD-RAM. (5) If the cursor is displayed, moves the cursor to the left most character in the top line (upper line). (6) Sets the address counter (ACC) to increment on the each access of DD-RAM or CG-RAM. 6.2.2 Cursor Home
D7 0 RS = 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 * Hex. Range 02H or 03H
This instruction (1) Clears the contents of the address counter (ACC) to 00H. (2) Sets the address counter (ACC) to point to the DD-RAM. (3) Sets the display for zero character shifts (returns original position). (4) If the cursor is displayed, moves the left most character in the top line (upper line). 6.2.3 Entry Mode Set
D7 0 RS = 0 D6 0 D5 0 D4 0 D3 0 D2 1 D1 I/D D0 S Hex. Range 04H ~ 07H
The I/D bit selects the way in which the contents of the address counter (ACC) are modified after every access to DD-RAM or CG-RAM. * I/D = 1: The address counter (ACC) is increased. * I/D = 0: The address counter (ACC) is decreased. The S bit enables display shift, instead of cursor shift, after each write to the DD-RAM. * S = 1: Display shift enabled. * S = 0: Cursor shift enabled. The direction in which the display is shifted is opposite in sense to that of the cursor. For example, if S=0 and I/D=1, the cursor would shift one character to the right after a MPU writes to DD-RAM. However if S=1 and I/D=1, the display would shift one character to the left and the cursor would maintain its position on the panel. Similarly writing the CG-RAM always shift the cursor. Also both lines are shifted simultaneously. *Cursor Move and Display Shift by the "Entry Mode Set"
I/D 0 1 0 1 S 0 0 1 1 After writing the DD-RAM data Cursor moves one character to the left Cursor moves one character to the right Display shifts one character to the right without cursor Display shifts one character to the left without cursor After reading the DD-RAM data Cursor moves one character to the left Cursor moves one character to the right Cursor moves one character to the left Cursor moves one character to the right
Page - 13 of 17
2X20 LCD Compatible VFD Module 6.2.4 Display ON/OFF
D7 0 RS = 0 D6 0 D5 0 D4 0 D3 1
20T202DA1E (Rev. 3.0)
D2 D
D1 C
D0 B
Hex. Range 08H ~ 0FH
This instruction controls various features of the display. * D = 1: Display ON, D = 0: Display OFF. * C = 1: Cursor ON, C = 0: Cursor OFF. * B = 1: Blinking ON, B = 0: Blinking OFF. (Blinking is achieved by alternating between a normal and all on display of a character. The cursor blinks with frequency of about 1.0 Hz and DUTY 50%.) 6.2.5 Cursor/Display Shift
D7 0 RS = 0 D6 0 D5 0 D4 1 D3 S/C D2 R/L D1 * D0 * Hex. Range 10H ~ 1FH
This instruction shifts the display and/or moves the cursor one character to the left or right without writing DD-RAM. The S/C bit selects movement of the cursor or movement of both the cursor and the display. * S/C = 1: Shift both cursor and display * S/C = 0: Shift cursor only The R/L bit selects left ward or right ward movement of the display and/or cursor. * R/L = 1: Shift one character right * R/L = 0: Shift one character left *Cursor or Display Shift S/C R/L Cursor Shift Display Shift 0 0 Move one character to the left No shift 0 1 Move one character to the right No shift 1 0 Shift one character to the left Shift one character to the left 1 1 Shift one character to the Shift one character to the right 6.2.6 Function Set
D7 0 RS = 0 D6 0 D5 1 D4 IF D3 N D2 * D1 BR1 D0 BR0 Hex. Range 20H ~ 3FH
This instruction sets the width of data bus line, the number of display line, and brightness control. This instruction initializes the system, and must be the first instruction executed after power-on. The IF bit selects a 8-bit or 4-bit bus width interface. * IF = 1: 8-bit CPU interface using DB7 to DB0 * IF = 0: 4-bit CPU interface using DB7 to DB4 (This module should be always chosen by 4-bit CPU interface). The N bit selects between 1-line or 2-line display. * N = 1: Select 2 line display (Using anode output A1 to A80) * N = 0: Select 1 line display (Using anode output A1 to A40. A41 to A80 fixed Low level). BR1, BR0 flag controls the brightness of VFD by modulating pulse width of Anode output as follows. * BR0, BR1 = (0, 0): Brightness = 100%, (0, 1): Brightness = 75%, (1, 0): Brightness = 50%, (1, 1): Brightness = 25%.
Page - 14 of 17
2X20 LCD Compatible VFD Module 6.2.7 Set CG-RAM Address
D7 0 RS = 0 D6 1 D5 D4 D3
20T202DA1E (Rev. 3.0)
D2 ACG
D1
D0
Hex. Range 40H ~ 7FH
This instruction: (1) Load a new 6-bit address into the address counter (ACC). (2) Sets the address counter (ACC) to address CG-RAM. Once "Set CG-RAM Address" has been executed, the contents of the address counter (ACC) will be automatically modified after every access of CG-RAM, as determined by the "Entry Mode Set" instruction". The active width of the address counter (ACC), when it is addressing CG-RAM, is 6 bits, so the counter will wrap around to 3FH from 00H if more than 64 bytes of data are written into CG-RAM. 6.2.8 Set DD-RAM Address
D7 1 RS = 0 D6 D5 D4 D3 ADD D2 D1 D0 Hex. Range 80H ~ A7H for 1st Line C0H ~ E7H for 2nd Line
This instruction: (1) Loads a new 7-bit address into the address counter (ACC). (2) Sets the address counter (ACC) to point to the DD-RAM. Once the "Set DD-RAM Address" instruction has been executed, the contents of the address counter (ACC) will be automatically modified after each access of DD-RAM, as selected by the "Entry Mode Set" instruction. *Valid DD-RAM Address Ranges Number of Character Address Range 1st line 40 00H to 27H 2nd line 40 40H to 67H 6.2.9 Write Data to CG or DD-RAM
D7 RS = 1 D6 D5 D4 D3 D2 D1 D0 Hex. Range 00H ~ 0FH for CG-RAM Code 10H ~ FFH for CG-ROM Code Character Code (Write-in)
This instruction writes 8-bit binary data (D7 to D0) into CG-RAM or DD-RAM. To write into CG-RAM or DD-RAM is determined by the previous specification of the CG-RAM or DD-RAM address setting. After a write, the address is automatically increased or decreased by 1 according to the entry mode. The entry mode also determines the display shift. When data is written to the CG-RAM (UDF character data), the D7, D6 and D5 bits are not displayed as characters.
Page - 15 of 17
2X20 LCD Compatible VFD Module
20T202DA1E (Rev. 3.0)
6.3 Example of Initialization After Power ON (4-bits data, date increment etc.)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Wait for 100 us after Power ON Function set: - Data length: 8 bits - Display line No.: 2 lines - Brightness: 100% CG-RAM address set to 00H
0 0
0 0
0 0 *
0 1 * * ......
1 0 * *
1 0
1 0
* 0
0 0
0 0
D4 D3 D2 D1 D0 Writes data in CG-RAM in 4-bit mode, every bytes data needs D4 D3 D2 D1 D0 to transfer twice in serial port. ...... 128 bytes data are needed in the serial port if 8 characters of D4 D3 D2 D1 D0 CG-RAM were defined one time. 0 0 0 0 0 DD-RAM address set to 00H (the first column of upper line) Writes data into DD-RAM (choose the character codes to display in upper line) Totally 16 bytes in the upper line (16 characters) DD-RAM address set to 40H (the first column of lower line) Writes data into DD-RAM (choose the character codes to display in lower line) Totally 16 bytes in the lower line (16 characters) Display ON, Cursor OFF, Cursor blink OFF
1
0
*
* 0 0 1
* 0
* 0
D7 D6 D5 D4 D3 D2 D1 D0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ...... ......
D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 0 0 0 0
D7 D6 D5 D4 D3 D2 D1 D0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ...... ......
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 1 0 0
* Note) "Dn" is the binary data to be written-in. Power ON Function Set Display ON/OFF CG-RAM Address Set Character Code Write-in CG-RAM Data Define DD-RAM Address Set
Fig.-13 Example of Initialization after Power ON
Page - 16 of 17
2X20 LCD Compatible VFD Module
20T202DA1E (Rev. 3.0)
Appendix-1. Character Font Table (CG-ROM and CG-RAM Address Codes)
Upper D7 Nibble D6 Lower Nibble
D5 D4
D3 D2 D1 D0 00000 00011 00102 00113 01004 01015 01106 01117 10008 10019 1010A 1011B 1100C 1101D 1110E 1111F
0 0 0 0 0
CG-RAM (#1) CG-RAM (#2) CG-RAM (#3) CG-RAM (#4) CG-RAM (#5) CG-RAM (#6) CG-RAM (#7) CG-RAM (#8) CG-RAM (#1) CG-RAM (#2) CG-RAM (#3) CG-RAM (#4) CG-RAM (#5) CG-RAM (#6) CG-RAM (#7) CG-RAM (#8)
. . . . . . .
0 0 0 1 1
O. . . OO . . O OO . O OO O O OO . OO . . O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0 0 1 0 2
. . . . . . . O O O O . . O . . . . . . . . . . . . . . . . . . . . . O O O . . . . . . . . . . . . . . . . . . . . . . . . .
0 0 1 1 3
. OOO . O. . .O O . . OO O.O.O OO . . O O. . .O . OOO . . . . . . . . .O. OO . .O. .O. .O. .O. OOO . . . . . . .
0 1 0 0 4
. OOO . O. . .O . . . .O . OO . O O.O.O O.O.O . OOO . . .O. . .O.O. O. . .O O. . .O O OOO O O. . .O O. . .O O OOO . O. . .O O. . .O O OOO . O. . .O O. . .O O OOO . . OOO . O. . .O O. . . . O. . . . O. . . . O. . .O . OOO . O OO . . O. .O. O. . .O O. . .O O. . .O O. .O. O OO . . O OOO O O. . . . O. . . . O OOO . O. . . . O. . . . O OOO O O OOO O O. . . . O. . . . O OOO . O. . . . O. . . . O. . . . . OOO . O. . .O O. . . . O . OO O O. . .O O. . .O . OOO O O. . .O O. . .O O. . .O O OOO O O. . .O O. . .O O. . .O . . . . . . . OOO .O. .O. .O. .O. .O. OOO . . . . . . .
0 1 0 1 5
O OOO . O. . .O O. . .O O OOO . O. . . . O. . . . O. . . . . OOO . O. . .O O. . .O O. . .O O.O.O O . . OO . OO . O O OOO . O. . .O O. . .O O OOO . O.O. . O. .O. O. . .O . OOO . O. . .O O. . . . . OOO . . . . .O O. . .O . OOO . O OOO O . .O. . . .O. . . .O. . . .O. . . .O. . . .O. . O. . .O O. . .O O. . .O O. . .O O. . .O O. . .O . OOO . O. . .O O. . .O O. . .O O. . .O O. . .O .O.O. . .O. . O. . .O O. . .O O. . .O O.O.O O.O.O O.O.O .O.O. O. . .O O. . .O .O.O. . .O. . .O.O. O. . .O O. . .O O. . .O O. . .O O. . .O .O.O. . .O. . . .O. . . .O. . O OOO O . . . .O . . .O. . .O. . .O. . . O. . . . O OOO O . . . . . . . OOO O. . O. . O. . O. . O. . OOO . . . . . . . . . . . . . .
0 1 1 0 6
O. . .O. . .O ... ... ... ... . . . . . . .
0 1 1 1 7
..... ..... O OO O . O. . .O O OO O . O. . . . O. . . . ..... ..... . OO . O O . . OO . OO OO . . . .O . . . .O ..... ..... O . OO . OO . . O O. . . . O. . . . O. . . . ..... ..... . OO O . O. . . . . OO O . . . . .O O OO O . .O. . . .O. . . O OO . . .O. . . .O. . . .O. .O . . OO . ..... ..... O. . .O O. . .O O. . .O O . . OO . OO . O ..... ..... O. . .O O. . .O O. . .O .O.O. . .O. . ..... ..... O. . .O O. . .O O.O.O O.O.O .O.O. ..... ..... O. . .O .O.O. . .O. . .O.O. O. . .O ..... ..... O. . .O O. . .O . OO OO . . . .O . OO O . ..... ..... O OO OO . . .O. . .O. . .O. . . O OO OO . . . . . . . . . . . . . . . . . . . . . . .O .O. .O. O. . .O. .O. . .O . . . . . . . O O O . O O O . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 0 0 0 8
OOO OO O. . .O O. . . . OOO O . O. . .O O. . .O OOO O . . OO O . .O.O. .O.O. .O.O. O. .O. OOO OO O. . .O O.O.O O.O.O . OO O . . .O. . . OO O . O.O.O O.O.O OOO O . . . . .O . . . .O . . OO . . . . .O . . . .O OOO O . O. . .O O. . .O O . . OO O.O.O OO . . O O. . .O O. . .O .O.O. . .O. . O. . .O O . . OO O.O.O OO . . O O. . .O . OO OO . .O.O . .O.O . .O.O . .O.O O.O.O .O. .O OOO OO O. . .O O. . .O O. . .O O. . .O O. . .O O. . .O O. . .O O. . .O O. . .O .O.O. . .O. . .O. . . O. . . . O. . .O O. . .O O. . .O O. . .O O. . .O OOO OO . . . .O O. . .O O. . .O O. . .O . OO OO . . . .O . . . .O . . . .O O.O.O O.O.O O.O.O O.O.O O.O.O O.O.O OOO OO O.O.O O.O.O O.O.O O.O.O O.O.O OOO OO . . . .O OO . . . .O. . . .O. . . . OO O . .O. .O .O. .O . OO O . O. . O. . O. . OO . O.O O.O OO . . . . . . . . O O O O O O O
1 0 0 1 9
..... ..... .O. .O O.O.O O. .O. O. .O. . OO . O . .O. . . . OO . . .O.O . .O.O . .O. . OOO . . OOO . . OOO OO O. . .O O. . . . O. . . . O. . . . O. . . . O. . . . ..... ..... OOO OO .O.O. .O.O. .O.O. O . . OO OOO OO .O. . . . .O. . . . .O. . .O. . .O. . . OOO OO ..... ..... . OO OO O. .O. O. .O. O. .O. . OO . . . . OO . . .O.O . . O OO . .O.O OOO . O OO . OO . . . OO ..... . . . .O . OO O . O.O. . . .O. . . .O. . . . .O. . .O. . . OO O . . OO O . . OO O . OOO OO . .O. . ..... . OO O . O. . .O O. . .O OOO OO O. . .O O. . .O . OO O . . OO O . O. . .O O. . .O O. . .O O. . .O .O.O. OO . OO . . OO . .O. .O . .O. . .O.O. O. . .O O. . .O . OO O . ..... ..... . O . OO O.O.O OO . O . ..... ..... ..... .O.O. OOO OO OOO OO OOO OO . OO O . . .O. . ..... ..... . OO O . O. . . . . OO . . O. . .O . OO O . . OO O . O. . .O O. . .O O. . .O O. . .O O. . .O O. . .O
1 0 1 0 A
OO OO OO OO OO OO OO . . . . . . . . . . . . . . . . . . . . . . O . O O O O OO OO OO OO OO OO OO . . . . . . . . . . . . . .
1 0 1 1 B
. OO . O. .O O. .O O. .O . OO . .... .... . . . . . . .
1 1 0 0 C
.O. . . . .O. . .O.O. O. . .O OO OOO O. . .O O. . .O . . .O. . .O. . . O OO . O. . .O OO OOO O. . .O O. . .O . .O. . .O.O. . O OO . O. . .O OO OOO O. . .O O. . .O . OO . O O . OO . . O OO . O. . .O OO OOO O. . .O O. . .O .O.O. ..... . O OO . O. . .O OO OOO O. . .O O. . .O . O OO . .O.O. . O OO . O. . .O OO OOO O. . .O O. . .O . . OOO . OO . . O.O. . O . OOO OO O . . O.O. . O . OOO . O OO . O. . .O O. . . . O. . .O . O OO . . .O. . OO O . . .O. . . . .O. . OO OOO O. . . . OO OO . O. . . . OO OOO . . .O. . .O. . OO OOO O. . . . OO OO . O. . . . OO OOO . .O. . .O.O. OO OOO O. . . . OO OO . O. . . . OO OOO .O.O. ..... OO OOO O. . . . OO OO . O. . . . OO OOO . . . . . . . . . . . . . . . . . . . . . . . . . . . . O. . .O. O OO .O. .O. .O. O OO . .O .O. O OO .O. .O. .O. O OO .O. O.O O OO .O. .O. .O. O OO O.O ... O OO .O. .O. .O. O OO . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 1 0 1 D
. O OO . .O. .O .O. .O OO O . O .O. .O .O. .O . O OO . . OO . O O . OO . O. . .O OO . . O O.O.O O . . OO O. . .O .O. . . . .O. . . O OO . O. . .O O. . .O O. . .O . O OO . . . .O. . .O. . . O OO . O. . .O O. . .O O. . .O . O OO . . .O. . .O.O. . O OO . O. . .O O. . .O O. . .O . O OO . . OO . O O . OO . . O OO . O. . .O O. . .O O. . .O . O OO . .O.O. ..... . O OO . O. . .O O. . .O O. . .O . O OO . ..... O. . .O .O.O. . .O. . .O.O. O. . .O ..... . O OO . . .O. . . O OO . O.O.O . O OO . . .O. . . O OO . .O. . . . .O. . O. . .O O. . .O O. . .O O. . .O . O OO . . . .O. . .O. . O. . .O O. . .O O. . .O O. . .O . O OO . . .O. . .O.O. ..... O. . .O O. . .O O. . .O . O OO . .O.O. ..... O. . .O O. . .O O. . .O O. . .O . O OO . . . .O. . .O. . O. . .O .O.O. . .O. . . .O. . . .O. . OO . . . . O OO . .O. .O .O. .O . O OO . .O. . . OO O . . . . OO . .O. .O .O. .O . O OO . .O. .O .O. .O O . OO .
1 1 1 0 E
.O. . . . .O. . . O OO . . . . .O . O OOO O. . .O . O OOO . . .O. . .O. . . O OO . . . . .O . O OOO O. . .O . O OOO . .O. . .O.O. . O OO . . . . .O . O OOO O. . .O . O OOO . OO . O O . OO . . O OO . . . . .O . O OOO O. . .O . O OOO .O.O. ..... . O OO . . . . .O . O OOO O. . .O . O OOO . O OO . .O.O. . O OO . . . . .O . O OOO O. . .O . O OOO ..... ..... OO . O . . .O.O . O OOO O.O. . . O . OO ..... . O OO . O. . . . O. . .O . O OO . . .O. . . OO . . .O. . . . .O. . . O OO . O. . .O OO OOO O. . . . . O OO . . . .O. . .O. . . O OO . O. . .O OO OOO O. . . . . O OO . . .O. . .O.O. . O OO . O. . .O OO OOO O. . . . . O OO . .O.O. ..... . O OO . O. . .O OO OOO O. . . . . O OO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O. . .O. ... OO . .O. .O. O OO . .O .O. ... OO . .O. .O. O OO .O. O.O ... OO . .O. .O. O OO ... O.O ... OO . .O. .O. O OO . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 1 1 1 F
.O.O. . .O. . .O.O. . . . .O . O OOO O. . .O . O OO . . OO . O O . OO . ..... O . OO . OO . . O O. . .O O. . .O .O. . . . .O. . ..... . O OO . O. . .O O. . .O . O OO . . . .O. . .O. . ..... . O OO . O. . .O O. . .O . O OO . . .O. . .O.O. ..... . O OO . O. . .O O. . .O . O OO . . OO . O O . OO . ..... . O OO . O. . .O O. . .O . O OO . .O.O. ..... ..... . O OO . O. . .O O. . .O . O OO . ..... . .O. . ..... OO OOO ..... . .O. . ..... . . .O. . .O. . . O OO . O.O.O . O OO . . .O. . .O. . . .O. . . . .O. . O. . .O O. . .O O. . .O O . . OO . OO . O . . .O. . .O. . O. . .O O. . .O O. . .O O . . OO . OO . O . .O. . .O.O. ..... O. . .O O. . .O O . . OO . OO . O .O.O. ..... O. . .O O. . .O O. . .O O . . OO . OO . O . . .O. . .O. . O. . .O O. . .O . O OOO . . . .O . O OO . . . . . . . . OO . . .O. . . OO . .O.O . OO . .O. . O OO .
. . .O . . OO . O OO OO OO . O OO . . OO . . .O .O O. OO .. .. .. .. OO .O O. .. .. .. .. . . . . . . . . . . . . . .
..... ..... . OO O . . . . .O . OO OO O. . .O . OO OO O. . . . O. . . . O . OO . OO . . O O. . .O O. . .O O OO O . ..... ..... . OO O . O. . . . O. . . . O. . .O . OO O . . . . .O . . . .O . OO . O O . . OO O. . .O O. . .O . OO OO ..... ..... . OO O . O. . .O O OO OO O. . . . . OO O . . . OO . .O. .O .O. . . O OO . . .O. . . .O. . . .O. . . ..... ..... . OO OO O. . .O . OO OO . . . .O . OO O . O. . . . O. . . . O . OO . OO . . O O. . .O O. . .O O. . .O . . . . . . . .O. ... .O. OO . .O. .O. OO O . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. .O. . . .O. . OOO OO . .O. . . .O. . ..... OOO OO . OO . O. .O . .O. .O. . OOO O .... .... OOO . . . .O . OO . . . .O OOO . .... .... . . . . . . . . . . . . . .
.O O. OO .. .. .. .. OO .O O. .. .. .. ..
O O O . . . .
. OOO . O. . .O . . . .O . . .O. . .O. . .O. . . O OOO O O OOO O . . .O. . .O. . . . .O. . . . .O O. . .O . OOO . . . .O. . . OO . .O.O. O. .O. O OOO O . . .O. . . .O. O OOO O O. . . . O OOO . . . . .O . . . .O O. . .O . OOO . . . OO . .O. . . O. . . . O OOO . O. . .O O. . .O . OOO . O OOO O O. . .O . . . .O . . .O. . .O. . . .O. . . .O. . . OOO . O. . .O O. . .O . OOO . O. . .O O. . .O . OOO . . OOO . O. . .O O. . .O . OOO O . . . .O . . .O. . OO . . . . . . . . . . . . . . . . .. OO OO .. OO OO .. .. OO OO .. OO .O O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. .O. . . OO O . O.O. . O.O. . O.O.O . OO O . . .O. . . . OO . .O. . . .O. . . OOO . . .O. . . .O. .O O . OO . ..... O. . .O . OO O . .O.O. . OO O . O. . .O ..... O. . .O .O.O. OOO OO . .O. . OOO OO . .O. . . .O. . . . . . . . . . . . . . . . O O O . O O O . . . . . . . . . . . . . .
.O.O. .O.O. O OOO O .O.O. O OOO O .O.O. .O.O. . .O. . . OOO O O.O. . . OOO . . .O.O O OOO . . .O. . OO . . . OO . . O . . .O. . .O. . .O. . . O . . OO . . . OO . OO . . O. .O. O.O. . .O. . . O.O.O O. .O. . OO . O . . . . . . . . . . . . . . . . . . . . . OO .O O. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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